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NCP3123 Dual 3.0 A, Step-Down DC/DC Switching Regulator
The NCP3123 is a dual buck converter designed for low voltage applications requiring high efficiency. This device is capable of producing an output voltage as low as 0.8 V. The NCP3123 provides dual 3.0 A switching regulators with an adjustable 200 kHz - 2200 kHz switching frequency. The switching frequency is set by an external resistor. The NCP3123 also incorporates an auto-tracking and sequencing feature. Protection features include cycle-by-cycle current limit and undervoltage lockout (UVLO). The NCP3123 comes in a 32-pin QFN package.
Features http://onsemi.com MARKING DIAGRAM
1 1 32 NCP3123 AWLYYWWG G
* * * * * * * * * * *
Input Voltage Range from 4.5 V to 13.2 V 12 Vin to 5.0 Vout = 85% Efficiency Min @ 3.0 A 200-2200 kHz Operation Stable with Low ESR Ceramic Output Capacitor 0.8 1.5% FB Reference Voltage External Soft-Start Out of Phase Operation of OUT1 & OUT2 Auto-Tracking and Sequencing Enable/Disable Capability Hiccup Overload Protection Low Shutdown Power (Iq < 100 mA)
QFN32 CASE 488AM
NCP3123 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 40 of this data sheet.
Typical Applications
* Set-Top Boxes, Portable Applications, Networking and *
Telecommunications DSP/mP/FPGA Core
VIN RVIN FB1 R_TRACK PG1 Enable Disable Enable Disable EN2 PG2 EN1 R14 R24 C3 AVIN GND PG1 PG2 EN1 SEQ1 EN2 SEQ2 COMP2 COMP1 AGND AGND TRACK1,2 FB2 RT SW2 SS1
OUT1 SW1 L11 D11 R11
C11
NCP3123
GND VIN R12 C1 GND L21 D21 C12 GND R22 R13 C13 GND GND GND C2 GND GND OUT2 GND
GND
SS2
R21
C21
RT
C22 R23 GND C23 GND
GND
Figure 1. Typical Application Circuit
(c) Semiconductor Components Industries, LLC, 2008
October, 2008 - Rev. 1
1
Publication Order Number: NCP3123/D
NCP3123
0 .1. ref Falling comp SHDN 1 PG 1
0 .9 . ref
pg 1
HS protection 1 Delay
VIN
COMP 1 Error Amplifier FB 1 EOTA 1 PWM 0o
R CON TR OL LOGIC 1 S HS1
SW 1
1V 10 u SS 1 TRACK 1 Soft Start & Tracking Control (MUX1) 10 u OSCILLATOR RT SEQ1 EN 1 Power Sequencing 1 SHDN 1 SHDN2 STAR TU P UVL O TH ER MAL SH U TD OWN ref (0.8 V) FB1 0. 5V Overload Protection Signal Voltage AGND SHDN 1 AVIN Reference 0. 8V ref (0 .8V ) ref (0.8 V) AVIN GND 1 SS 1
EN 2 SEQ 2 SS2
Power Sequencing 2 1V 10u SS 2 Soft Start & Tracking Control (MUX2) 10u FB2 0 .5V 180o Error Amplifier EOTA 2 PWM R
SHDN1 SHDN2 SHDN 2
GND 2
TRACK 2
HS protection 2 VIN Overload Protection S CON TR OL LOGIC 2 HS 2
COMP 2
FB 2
SW 2
pg 2 0 .9 . ref
PG 2 Delay 0 .1. ref Falling comp SHDN 2
Figure 2. Block Diagram
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NCP3123
PIN DESCRIPTION
Pin 1, 31, 32 2-7 8 - 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol SW1 VIN SW2 GND2 SS2 COMP2 AGND FB2 RT TRACK 2 TRACK 1 SEQ2 EN2 SEQ1 EN1 PG2 PG1 AVIN FB1 AGND COMP1 SS1 GND1 Exposed Pad (GND) Description Switch node of Channel 1. Connect an inductor between SW1 and the regulator output. Input power supply voltage pins. These pins should be connected together to the input signal supply voltage pin. Switch node of Channel 2. Connect an inductor between SW2 and the regulator output. Power ground for Channel 2 Soft-start control input for Channel 2. An internal current source charges an external capacitor connected to this pin to set the soft-start time. Compensation pin of Channel 2. This is the output of the error amplifier and inverting input of the PWM comparator. Analog ground; connect to GND1 and GND2. Feedback Pin. Used to set the output voltage of Channel 2 with a resistive divider from the output. Resistor select for the oscillator frequency. Connect a resistor from the RT pin to AGND to set the frequency of the master oscillator. Leave this pin floating, for 200 kHz operation. Tracking input for Channel 2. This pin allows the user to control the rise time of the second output. This pin must be tied high in the normal operation (except in the tracking mode). Tracking input for Channel 1. This pin allows the user to control the rise time of the first output. This pin must be tied high in the normal operation (except in the tracking mode). Sequence pin for Channel 2. I/O used in power sequencing. Connect SEQ to EN for normal operation of a standalone device. Enable input for Channel 2. Sequence pin for Channel 1. I/O used in power sequencing. Connect SEQ to EN for normal operation of a standalone device. Enable input for Channel 1. Power good, open-drain output of Channel 2. Output logic is pulled to ground when the output is less than 90% of the desired output voltage. Tied to an external pull-up resistor. Leave this pin floating, if not used. Power good, open-drain output of Channel 1. Output logic is pulled to ground when the output is less than 90% of the desired output voltage. Tied to an external pull-up resistor. Leave this pin floating, if not used. Input signal supply voltage pin. Feedback Pin. Used to set the output voltage of Channel 1 with a resistive divider from the output. Analog ground. Connect to GND1 and GND2. Compensation pin of Channel 1. This is the output of the error amplifier and inverting input of the PWM comparator. Soft-start/stop control input for Channel 1. An internal current source charges an external capacitor connected to this pin to set the soft-start time. Power ground for Channel 1. The exposed pad at the bottom of the package is the electrical ground connection of the NCP3123. This node must be tied to ground.
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NCP3123
MAXIMUM RATINGS
Characteristics Power Supply Voltage Input Signal Supply Voltage Input SW Pin Voltage EN Pin Voltage Input SEQ Pin Voltage Output PG Pin Voltage All Other Pins Thermal Resistance, Junction-to-Ambient (Note 1) Storage Temperature Range Junction Operating Temperature (Note 2) Symbol VVIN VAVIN VSW VEN VSEQ VPG - RqJA TSTG TJ Min -0.3 -0.3 -0.7 -5V for < 50 ns -0.3 -0.3 -0.3 -0.3 50 -55 to +150 -40 to +150 Max 15 15 VVIN 8.0 8.0 5.5 5.5 V V C/W C C Unit V V V V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. RqJA on a 100 x 100 mm PCB with two solid 1 oz ground planes. 2. The maximum package power dissipation limit must not be exceeded
PD +
TJ
(max) * T A
R qJA
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NCP3123
ELECTRICAL CHARACTERISTICS (-40C < TJ < 125C, TJ = 25C for typical values, VAVIN =12 V, VVIN =12 V, unless otherwise
noted. RT = open kW) Characteristic RECOMMENDED OPERATING CONDITIONS Input Voltage Range SUPPLY CURRENT Quiescent Supply Current Shutdown Supply Current UNDERVOLTAGE LOCKOUT UVLO Threshold UVLO Hysteresis SWITCHING REGULATOR Minimum Duty Cycle Maximum Duty Cycle High Side MOSFET RDS(on) High Side Leakage Current High Side Switch Current Limit Set Point Current Loop Transient Response FB VFB Feedback Voltage TJ = 25C TJ = -40 to 125C, 4.5 V < VIN < 13.2V 0.788 0.784 0.8 - 0.812 0.816 V Comp = 0.6 V Comp = 2.6 V ISW = 0.5 A, TJ = 25C VEN = 0V, VSW = 0V (Note 3) (Note 4) 3.5 4.15 100 90 250 10 4.8 0 % % mW mA A nsec VIN Rising Edge VIN Falling Edge 3.9 0.15 4.3 4.1 0.20 4.5 0.25 V V VEN = H, VFB = 1.0 V No Switching, PG open VEN = 0 V, PG open 5.0 7.0 100 mA mA 4.5 13.2 V Conditions Min Typ Max Unit
OSC Oscillator Frequency TJ = 25C, TJ = -40C to 125C TJ = 25C, TJ = -40C to 125C (RT = 52.3 kW) Standard Oscillator Frequency Range TRANSCONDUCTANCE ERROR AMPLIFIER (GM) Transconductance DC Gain Unity Gain Bandwidth Output Sink Current Output Source Current Input Bias Current Comp Pin Operating Voltage Range SOFT-START Soft-Start Period Soft-Start Voltage Range Soft-Start Current Source Charging, VSS = 1 V Discharging, VSS = 1 V VFB < 0.8 V, CS = 0.1 mF 0 6.0 6.0 8.0 8.0 10 VFB 12 12 ms V mA mA (Note 4) (Note 4) (Note 4) VFB = 1.0 V, Vcomp = 1.5 V VFB = 0.6 V, Vcomp = 1.5 V VFB = 0.8 V (Note 4) 0.6 80 80 0.9 50 1.0 55 4.0 100 100 100 500 2.6 1.1 60 mS dB MHz mA mA nA V TJ = 25C 180 170 1913 200 200 200 2200 220 230 2530 2200 kHz kHz kHz kHz
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NCP3123
ELECTRICAL CHARACTERISTICS (-40C < TJ < 125C, TJ = 25C for typical values, VAVIN =12 V, VVIN =12 V, unless otherwise
noted. RT = open kW) Characteristic TRACK Tracking Voltage Range Tracking Voltage Offset Track Bias Current POWER GOOD PG Threshold PG Shutdown Mode Feedback Voltage Rising, EN Tied to SEQ, VPG = 3.3 V Feedback Voltage Falling, EN Tied to SEQ, VEN,SEQ = 0V, VPG = 3.3V Rising Edge of Vout Falling Edge of Vout I(PG) = 1 mA 45 VPG = 5.5 V 4.0 16 EN Tied to SEQ EN Tied to SEQ 2.0 0.8 1.0 90% VFB 10% VFB 15% VFB 20% VFB V V VTRACK = 0.6 V VTRACK = 0.6 V 100 0 VFB 15 500 V mV nA Conditions Min Typ Max Unit
PG Delay PG Low Level Voltage PG Hysteresis PG Leakage Current ENABLE/POWER SEQUENCING Enable Internal Pullup Current Sequence Internal Pulldown Current Enable Threshold High Sequence Threshold Low THERMAL SHUTDOWN Overtemperature Trip Point Hysteresis 3. DC value. 4. Guaranteed by design.
50 10 0.3
ms ms V mV mA
mA mA V V
(Note 4)
160 15
C C
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NCP3123
TYPICAL OPERATING CHARACTERISTICS
0.813 0.808 VOLTAGE (V) 0.803 0.798 0.793 0.788 0.783 -50 FREQUENCY (kHz) 2100 2080 2060 2040 2020 2000 1980 -25 0 25 50 75 100 125 1960 -50 -25 0 25 50 75 100 125 RT = 12 kW
TEMPERATURE (C)
TEMPERATURE (C)
Figure 3. Feedback Voltage vs. Temperature
216 211 FREQUENCY (kHz) 206 201 196 191 186 -50 CURRENT (mA) RT = open 6 5 4
Figure 4. High Switching Frequency vs. Temperature
1 Channel Disabled 3 2 1 0 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. Low Switching Frequency vs. Temperature
Figure 6. Quiescent Supply Current vs. Temperature
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NCP3123
TYPICAL OPERATING CHARACTERISTICS
100 90 80 CURRENT (mA) 70 RDS(on) (W) 60 50 40 30 20 10 0 -50 0.20 0.15 -50 0.30 0.25 0.35 0.40
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 7. Shutdown Supply Current vs. Temperature
4.50 4.45 CURRENT (A) VOLTAGE (V) 4.40 4.35 4.30 4.25 4.20 -50 4.4 4.3 4.2 4.1 4.0 3.9 3.8 -50
Figure 8. RDS(on) vs. Temperature
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. UVLO - Rising Threshold vs. Temperature
4.20 4.15 CURRENT (mA) VOLTAGE (V) 4.10 4.05 4.00 3.95 3.90 -50 9.9 9.4 8.9 8.4 7.9 7.4 6.9 -50
Figure 10. Current Limit vs. Temperature
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. UVLO - Falling Threshold vs. Temperature
Figure 12. Soft-Start Charge Current vs. Temperature
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NCP3123
TYPICAL OPERATING CHARACTERISTICS
9.9 9.4 CURRENT (mA) VOLTAGE (mV) -25 0 25 50 75 100 125 8.9 8.4 7.9 7.4 6.9 -50 70 65 60 55 50 45 40 35 30 25 20 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Soft-Start Discharge Current vs. Temperature
15 10 VOLTAGE (mV) 5 0 -5 -10 -15 -50 VTRACK = 0.6 V 65 60 55 50 45 40 35 -50
Figure 14. Power Good Hysteresis vs. Temperature
-25
0
25
50
75
100
125
DELAY (ms)
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 15. Tracking Voltage Offset vs. Temperature
0.83 0.81 VOLTAGE (V) 0.79 0.77 0.75 0.73 0.71 -50 17 15 13 11 9 7 5 -50
Figure 16. Power Good Rising Delay vs. Temperature
-25
0
25
50
75
100
125
DELAY (ms)
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 17. Power Good Feedback Threshold vs. Temperature
Figure 18. Power Good Falling Delay vs. Temperature
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NCP3123
TYPICAL OPERATING CHARACTERISTICS
0.45 0.40 0.35 CURRENT (mA) -25 0 25 50 75 100 125 VOLTAGE (V) 0.30 0.25 0.20 0.15 0.10 0.05 0 -50 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 -50 -25 0 25 50 75 100 125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 19. Power Good Saturation Voltage vs. Temperature
12 10 CURRENT (mA) 8 Ids (mA) 6 4 2 0 20 19 18 17 16 15 14 13 12 11 10 -50
Figure 20. EN Internal Pull-up Current vs. Temperature
0
0.5
1.0
1.5
2.0
2.5 Vds (V)
3.0
3.5
4.0
4.5
5.0
-25
0
25
50
75
100
125
TEMPERATURE (C)
Figure 21. Power Good Current vs. Drain-to-Source Voltage
3.40 3.38 3.36 3.34 Vout (V) Vout (V) 3.32 3.30 3.28 3.26 3.24 3.22 3.20 Iout = 50 mA 3.318 3.315 3.312 3.309 3.306 3.303 3.3
Figure 22. SEQ Internal Pull-down Current vs. Temperature
Vin = 12 V
Vin = 5 V
5
7
9 Vin (V)
11
13
15
0
0.5
1.0
1.5 Iout (A)
2.0
2.5
3.0
Figure 23. NCP3123 Line Regulation
Figure 24. NCP3123 Load Regulation
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NCP3123
TYPICAL OPERATING CHARACTERISTICS
90 85 EFFICIENCY (%) 80 75 70 65 60 55 0 1400 kHz 200 kHz 12 V 95 90 200 kHz 85 500 kHz 750 kHz EFFICIENCY (%) 80 75 70 65 60 1.5 Iout (A) 2.0 2.5 3.0 55 0 500 kHz 750 kHz 1400 kHz 2200 kHz 12 V
2200 kHz 0.5 1.0
0.5
1.0
1.5 Iout (A)
2.0
2.5
3.0
Figure 25. NCP3123 Efficiency, Vin = 12 V, Vout = 3.3 V, 255C
0.50 0.45 0.40 0.35 0.30 0.25 0.20 3.5 3.0 OUTPUT CURRENT (A) 2.5 2.0 1.5 1.0 0.5 4 5 6 7 8 9 10 11 12 13 14 0 200 400
Figure 26. NCP3123 Efficiency, Vin = 12 V, Vout = 5 V, 255C
5.5 Vin 5.0 Vin
RDS(on) (W)
4.5 Vin
600 800 1000 1200 1400 1600 1800 2000 2200 FREQUENCY (kHz)
Vin = AVin (V)
Figure 27. RDS(on) vs. Input Voltage
3.5 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 FREQUENCY (kHz) 4.5 Vin 5.0 Vin MINIMUM INPUT VOLTAGE (V) 3.3 OUTPUT CURRENT (A) 5.5 Vin 6.6 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7
Figure 28. Maximum Currents vs. Operating Frequency due to Toff min limitations 3.3 Vout
5.6 200 400
600 800 1000 1200 1400 1600 1800 2000 2200 FREQUENCY (kHz)
Figure 29. Maximum Currents vs. Operating Frequency due to Toff min limitations 1.8 Vout
Figure 30. Minimum Input Voltage vs. Operating Frequency, 3A, 3.3 Vout
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NCP3123
TYPICAL OPERATING CHARACTERISTICS
5.7 MINIMUM INPUT VOLTAGE (V) 5.6 INPUT CURRENT (A) 5.5 5.4 5.3 5.2 5.1 5.0 4.9 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 FREQUENCY (kHz) 0 0 0.5 1.0 1.5 2.0 1.5 1.0 0.5 2.5
12 Vin Two outputs
12 Vin One output 2.0 2.5 3.0
OUTPUT CURRENT (A)
Figure 31. Minimum Input Voltage vs. Operating Frequency, 3A, 1.8 Vout
6 5 4 Vout (V) 3 2 1 0 4.5 2.5 A 3.0 A Vout (V) 0.1 A 0.5 A 1.0 A 1.5 A 2.0 A 3.5 3 2.5 2 1.5 1 0.5 4.75 5.0 5.25 5.5 5.75 6.0 6.25 6.5 6.75 0 4.5
Figure 32. Minimum Input Current 3.3 Vout
0.1 A 0.5 A 1.0 A 1.5 A 2.0 A 2.5 A
3.0 A
4.75
5.0 Vin (V)
5.25
5.5
Vin (V)
Figure 33. Minimum Input Voltage 5 Vout, 350 kHz
6 5 4 Vout (V) Vout (V) 3 2 1 0 4.5 1.5 A 2.0 A 5.0 5.5 6.0 Vin (V) 6.5 7.0 7.5 2.5 A 3.0 A 0.1 A 0.5 A 1.0 A 3.5 3 2.5 2 1.5 1 0.5 0 4.5
Figure 34. Minimum Input Voltage 3.3 Vout, 350 kHz
0.1 A 0.5 A 1.0 A 1.5 A 2.0 A 2.5 A
3.0 A
4.75
5.0
5.25 Vin (V)
5.5
5.75
6.0
Figure 35. Minimum Input Voltage 5 Vout, 2.1 MHz
Figure 36. Minimum Input Voltage 3.3 Vout, 2.1 MHz
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NCP3123
DETAILED DESCRIPTION
Introduction
The NCP3123 is a dual channel non-synchronous PWM voltage mode buck regulator. Each channel is identical and has a 3.0 A internal P-FET, compensation, feedback, programmable soft-start, enable and power good pins. These circuits also share the same input voltage, reference voltage, thermal shutdown, undervoltage detect and master oscillator. A simple auto-tracking and sequencing capability can be implemented using the SEQ/TRACK/SS pins. The fixed-frequency programmable architecture, driven from a common oscillator, ensures a 180 phase differential between channels. This 180 phase shift between the two channels reduces the common input capacitor requirement and improves the noise immunity. The NCP3123 switching frequency is set by an external resistor and is adjustable between 200-2200 kHz. This allows application optimization between efficiency and total solution size. The output voltage is fed back through an external resistor voltage divider to the FB input pin and compared with the reference voltage, then the voltage difference is amplified through the internal transconductance error amplifier. The output current of the transconductance error amplifier (OTA) is presented at the COMP node where an RC network compensates the regulation control system loop. The NCP3123 features a programmable soft-start function, which is implemented through the error amplifier and the external compensation capacitor. This feature prevents stress to the power components and limits output voltage overshoot during start-up.
Undervoltage Lockout (UVLO)
frequency of the NCP3123 is programmable from 200 kHz to 2200 kHz using an external resistor connected from the RT pin to ground. The oscillator works on the double frequency internally. Therefore, both channels have a 180 phase shift of the SW pins.
Out-of-Phase Operation
In out-of-phase operation, the turn-on of the second channel is delayed by half the switching cycle. This delay is supervised by the oscillator, which supplies a clock signal to the second channel which is 180 out of phase with the clock signal of the first channel. The advantages of out-of-phase synchronization are many. Since the input current pulses are interleaved with one another, the overlap time is reduced. The effect of this overlap reduction is to attenuate the input filter requirement, allowing the use of smaller components. Additionally, since peak current occurs during a shorter time period, emitted EMI is also reduced, thereby reducing shielding requirements.
Enable Input
Undervoltage lockout (UVLO) is provided to ensure that unexpected behavior does not occur when Vin is too low to support the internal rails and power the converter. In case the input voltage is higher than the UVLO threshold (4.3 V standard value, rising voltage), the step down converter operation can be started. This circuit has a 0.2 V hysteresis (typical). If the falling trip is activated, switching ceases and eventually the circuit turns off. When the input circuit is in this state, the currrent consumption is equal 5 mA (typical).
Fixed Frequency Operation
Pull the EN enable input high to enable the operation. Logic low on SEQ forces the NCP3123 into shutdown mode. Connect SEQ to EN for normal operation of a standalone device. In shutdown mode, the NCP3123 is turned off and the supply current is reduced to less than 100 mA. In case the enable function will not be required, EN and SEQ pin have to be pulled high or connected directly to Vin (max 8 V). Note: For proper operation of the NCP3123 circuit, no voltage may be pulled high on the output pins. The output capacitors should be discharged. If this condition is not observed when NCP3123 is enabled, the regulator does not start switching. This helps to prevent improper operation of the NCP3123 circuit due to the implemented tracking and sequencing features.
Soft-Start/Stop Control
The NCP3123 uses a constant frequency architecture for generating a PWM signal. During normal operation, the oscillator generates an accurate pulse at the beginning of each switching cycle to turn on the main switch. The main switch will be turned off when the ramp signal intersects with the output of the error amplifier (COMP pin voltage). Therefore, the switch duty cycle can be modified to regulate the output voltage to the desired value as line and load conditions change. The major advantage of fixed frequency operation is that the component selections, especially the magnetic component design, become very easy. The oscillator
This capacitor limits the maximum demand on the external power supply by controlling the inrush current peaks to charge the output capacitor and DC load and to attain smoothly increasing output voltage at start-up. A soft start circuit forces the error amplifier output to follow a prescribed voltage ramp when turning on and off. The output capacitor is discharged when Vin goes under the UVLO as thermal shutdown or overload detection occurs. The circuit input is presented as a voltage ramp generated by internal current sources tied to an external SS capacitor. The external capacitor on the soft-start node is charged/discharged by the 8.75 mA current from the constant current source, and the voltage on the SS node controls the OTA amplifier output voltage until the SS capacitor is charged/discharged to a voltage higher than 0.8 V.
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NCP3123
Power Good
The power good is an open drain and active high output that indicates when the output voltage has reached 90% (min) of the nominal output voltage. This output can be pulled up to the appropriate level with an external resistor. The power good comparator senses the voltage at the FB pin, which is a function of Vout. The power good output transistor behavior is shown in the "Typical Operating Characteristics" section. The PG pin is held low during a soft-start. Once a soft-start is completed, the PG goes high if there are no faults and no delays associated with it.
Current Limit
peak switch current in excess of 3.5 A (minimum). Current limiting is implemented by monitoring the high-side P-channel switch current during conduction with a current limit comparator. When the peak of the switching current reaches the current limit, the power switch turns off.
Hiccup Overload Protection (OLM - Over Load Mode)
The NCP3123 protects a power system if overcurrent occurs. The NCP3123 contains pulse-by-pulse current limiting to protect the power switch and external components. The current through each channel is continuously monitored. The current limit is set to allow
Hiccup mode is a method of protecting the power supply from damage during overload conditions. Within normal operation, the external soft-start capacitor is pulled up by a current source that delivers 8.75 mA to the SS pin capacitor. The soft-start capacitor continues to charge until it reaches the saturation voltage of the current source, typically Vss = 4 V. When the overload condition is detected, the soft-start capacitor is discharged to 0.1 V and is again charged to 1 V. This is periodically repeated until the overload condition is detected. The transconductance error amplifier output is tied to ground when the soft-start capacitor is discharged.
Figure 37. Hiccup Overload Protection Thermal Shutdown
The NCP3123 has a thermal shutdown feature to protect the device from overheating when the die temperature exceeds 160C (typically). If the chip temperature exceeds the overtemperature shutdown trip point, the fault signal is activated. This will disable the step down converter operation, and the chip temperature will start to decrease.
When the chip temperature drops 15C below the overtemperature shutdown trip point, the fault signal is deactivated and the step down converter operation starts again with soft-start. The thermal event sends the device immediately into the OFF state. The currrent consumption is equal 5 mA (typical) if the thermal condition is reached.
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NCP3123
APPLICATION & DESIGN INFORMATION
Inductor
The output inductor may be the most critical component in the converter because it will directly affect the choice of other components and dictate both the steady state and transient performance of the converter. When choosing inductors, one might have to consider maximum load current, core and copper losses, component height, output ripple, EMI, saturation and cost. Lower inductor values are chosen to reduce the physical size of the inductor. A higher value cuts down the ripple current and core losses and allows more output current. In general, the output inductance value should be as low and the output inductor physically as small as possible to provide the best transient response and minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, an inductance value that is too low will result in very large ripple currents in the power components, resulting in increased dissipation and lower converter efficiency. A good standard for determining the inductance to use is to select the inductor peak-to-peak ripple current to be approximately 25% of the maximum switch current. Also, make sure that the inductor peak current is below the maximum switch current limit and the selected inductor type saturation current specification is higher than the peak current through the switch.
Table 1. Calculated Inductor Values
The maximum current in the inductor while operating in the continuous current mode is defined as the load current plus one half of the DIL currrent:
I LP + I LOAD ) 1 DI L 2
The inductance value can be calculated by:
L+ V OUT V IN * V OUT V IN @ DI L @ f OSC
Therefore, the inductor peak current, ILP, can be calculated by:
I LP + I LOAD ) V OUT V IN * V OUT 2 @ V IN @ L @ f OSC
where; ILOAD is the output load current VOUT is the output voltage VIN is the input voltage DIL is the peak-to-peak inductor ripple current fOSC is the switching frequency of the oscillator The choice of the appropriate inductor type depends not only on the calculated inductance value, saturation current rating and parasitic serial resistance, but also on the required physical dimensions, EMI requirements (shielded or open inductor) and the price. Examples of suitable inductors from various manufacturers are shown in the table below.
Calculated coils, I ripple peak-peak 20% f [kHz] Iout [A] 12 Vin to 7.5 Vout 12 Vin to 5 Vout 12 Vin to 3.3 Vout 5 Vin to 3.3 Vout 5 Vin to 2.5 Vout 5 Vin to 1.8 Vout 2A 3A 2A 3A 2A 3A 2A 2A 2A 3A 36 mH 24 mH 36 mH 24 mH 30 mH 20 mH 14 mH 16 mH 15 mH 10 mH 20 mH 14 mH 20 mH 14 mH 17 mH 12 mH 8 mH 9 mH 8.2 mH 5.5 mH 14 mH 10 mH 15 mH 10 mH 12 mH 8 mH 5.6 mH 6.3 mH 5.8 mH 3.8 mH 10 mH 6.3 mH 10 mH 6.5 mH 8 mH 5.4 mH 3.7 mH 4 mH 3.8 mH 2.6 mH 5 mH 3.3 mH 5.2 mH 3.5 mH 4.3 mH 2.9 mH 2 mH 2.2 mH 2 mH 1.4 mH 3.2 mH 2.2 mH 3.3 mH 2.2 mH 2.7 mH 1.8 mH 1.3 mH 1.4 mH 1.3 mH 0.9 mH 200 350 500 750 1400 2200
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Table 2. Inductor Examples
L [mH] 33 Part Number DO5010H-333 PF0382.333NL MSS1278-333 74458133 PF0552.333NL 22 DS5022P-223 P0648.223 74458122 MSS1246T-223 PF0382.223NL 15 DO3316P-153 P0751.153NL MSS1260T-153 74459115 74458115 10 DO3340P-103 DS5022P-103 7445610 74459010 DO3316P-103 P0751.103NL 9 8.2 6.8 5.6 P1169.123NL DS3316T-822 MSS1246-822 74456068 DO33165-562 74456056 DO5022P-562 5.0 3.3 MSS7341-502 DO3316P-332 DS5022P-332 Shielded/ Non-shielded N N S N S S N N S N N N S S N N S N S N N S N S N N N S S S S Irms [A] 3.0 3.1 3.1 3.0 3.7 3.1 3.3 3.5 3.14 3.5 3.1 3.0 3.5 3.5 4.0 3.5 3.9 3.3 3.9 3.5 3.8 3.5 4.15 4.67 3.8 4.65 4.0 4.1 4.7 4.7 3.3 DCR max [mW} 66 65 80 66 54.1 59 61 47 70 47 46 46 40 48 36 40 42 45 40 34 38 37 32 35 34 21 32 3 24 26 39 Manufacturer Coilcraft PULSE Coilcraft WE PULSE Coilcraft PULSE WE Coilcraft PULSE Coilcraft PULSE Coilcraft WE WE Coilcraft `Coilcraft WE WE Coilcraft PULSE PULSE Coilcraft Coilcraft WE Coilcraft WE Coilcraft Coilcraft Coilcraft Coilcraft Web www.coilcraft.com www.pulseeng.com www.coilcraft.com www.we-online.com www.pulseeng.com www.coilcraft.com www.pulseeng.com www.we-online.com www.coilcraft.com www.pulseeng.com www.coilcraft.com www.pulseeng.com www.coilcraft.com www.we-online.com www.we-online.com www.coilcraft.com www.coilcraft.com www.we-online.com www.we-online.com www.coilcraft.com www.pulseeng.com www.pulseeng.com www.coilcraft.com www.coilcraft.com www.we-online.com www.coilcraft.com www.we-online.com www.coilcraft.com www.coilcraft.com www.coilcraft.com www.coilcraft.com
Output Rectifier Diode
When the high-side switch is on, energy is stored in the magnetic field in the inductor. During off time, the internal MOSFET switch is off. Since the current in the inductor has to discharge, the current flows through the rectifying diode to the output. A Schottky diode is recommended due to low diode forward voltage and very short recovery times, which positively impacts the step down voltage converter's overall efficiency. Another choice could be fast recovery or ultra-fast recovery diodes. It should be noted that some types of these diodes with an abrupt turn-off characteristic may cause instability or EMI troubles.
The peak reverse voltage is equal to the maximum input voltage. The peak conducting current is clamped by the current limit of the NCP3123. Use of Schottky barrier diodes reduces diode reverse recovery input current spikes. For switching regulators operating at low duty cycles, it is beneficial to use rectifying diodes with somewhat higher RMS current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The average current can be calculated from:
I D(AVG) + I LOAD V IN * V OUT V IN
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NCP3123
Table 3. Schottky Diode Example
Part Number MBRA340T3G MBRS340T3G MBRS330T3G Description 3 A, 40 V Schottky Rectifier 3 A, 40 V Schottky Rectifier 3 A, 30 V Schottky Rectifier VRRM min [V] 40 40 30 VF max [V] 0.45 0.5 0.5 IO(rec) max [A] 3 3 3 SMA SMC SMC www.onsemi.com www.onsemi.com www.onsemi.com Package Web
The worst case of the diode average current occurs during maximum load current and maximum input voltage. The rectifying diodes should be placed close to the SW pin to avoid the possibility of ringing due to trace inductance.
Input Capacitor
The input current to the step down converter is discontinuous. The input capacitor has to maintain the DC input voltage and to sustain the ripple current produced by internal MOSFET switching. For stable operation of the switch mode converter, a low ESR capacitor is needed to prevent large voltage transients from appearing at the input. Therefore, ceramic capacitors are preferred, but the circuit works in a stable manner also with electrolytic capacitors. It must be located near the regulator and use short leads. Also, paralleling ceramic capacitors will increase the regulator stability. The RMS value of the input capacitor current ripple is:
I RMS + I LOAD D(1 * D)
principle consideration for the output capacitor is the ripple current induced by the switches through the inductor. It supplies the current to the load in DCM or during load transient and filters the output voltage ripple. For low output ripple voltage and good stability, low ESR output capacitors are recommended. The inductor ripple current acting against the ESR of the output capacitor is the major contributor to the output ripple voltage. An output capacitor has two main functions: it filters the output and provides regulator loop stability. The ESR of the output capacitor and the peak-to-peak value of the inductor ripple current are the main factors contributing to the output ripple voltage value. The output voltage ripple is given by the following equation:
DV OUT + V OUT V 1 @ 1 * OUT @ ESR ) V IN f SW @ L 8 @ f SW @ C OUT
The duty cycle is:
D+ V OUT ) V D V IN ) V D * V DSAT
where: ESR is the equivalent series resistance of the output capacitor. The output capacitor value can by expressed by:
C OUT + DI L 8 @ f SW @ DV OUT * DI L @ ESR
where: VD is the voltage drop across the rectifying diode and VDSAT is the switch saturation voltage on the power MOSFET. The equation reaches its maximum value with duty cycle = 0.5, where:
I RMS + I LOAD 2
Losses in the input capacitor can be calculated using the following equation:
P CIN + I RMS2 @ ESR CIN
These components must be selected and placed carefully to yield optimal results. Key specifications for output capacitors are their ESR (equivalent series resistance) and ESL (equivalent series inductance) values. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. For most applications, a 22 mF ceramic capacitor should be sufficient. X5R or X7R dielectrics ceramic capacitors are recommended.
Soft-Start Capacitor Selection
where: ESRCIN is the effective series resistance of the input capacitance. The input capacitor voltage ripple depends on the CIN capacitor value. Therefore, the input capacitor can be estimated by:
V V I LOAD C IN + @ OUT @ 1 * OUT V IN f SW @ DV IN V IN Output Capacitor
The soft-start time is programmed by an external capacitor connected from the SS pin to AGND, which can be calculated by:
C SS [ t SS @ 8.75 mA 0.8 V
where: - tSS is the soft-start/stop interval. Note: See the "Sequencing and Tracking" section on how to use this capacitor.
The output capacitor filters output inductor ripple current and provides low impedance for load current changes. The
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NCP3123
Output Voltage Programming
The controller will maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit is placed across the
Table 4. Output Voltage Setting
VOUT [V] R1 [kW] R2 [kW] 8 180 20 VOUT R1 VFB R2 7.5 360 43 6 130 20 5 68 13
feedback pin to VOUT, the controller will regulate the output voltage in proportion to the resistor divider network in order to maintain 0.8 V at the FB pin.
4 300 75
3.3 47 15
2.5 51 24
1.8 20 16
1.2 10 20
Figure 38. Feedback divider
The relationship between the resistor divider network and the output voltage is shown in the following equation:
R2 + R1 V REF V OUT * V REF
frequency operation because a higher frequency results in lower efficiency due to MOSFET gate charge losses. Additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents. The value of the oscillator resistor is designed to be linearly related to the switching period. There are two ways to determine the RT resistor value: by using the standard curve shown in Figure 39 or by using Table 5. The frequency on the RT pin will set the master oscillator. The actual operating frequency on each channel will be one-half the master oscillator.
200 180 160 RT [kOhm] 140 120 100 80 60 40 20 0 200 600 1000 1400 freq [kHz] 1800 2200
where: VREF is the circuit's internal voltage reference, which equals 0.8 V. Resistor R1 is selected based on a design trade-off between efficiency and output voltage accuracy. For high values of R1, there is less current consumption in the feedback network. However, the trade-off is output voltage accuracy due to the bias current in the error amplifier. Once R1 has been determined, R2 can be calculated.
Selecting the Switching Frequency
Selecting the switching frequency is a trade-off between component size and power losses. Operation at higher switching frequencies allows the use of smaller inductor and capacitor values. Nevertheless, it is common to select lower
Table 5. Switching Frequency Selection
Freq. [kHz] RT [kW] 200 open 300 316 400 154 500 100 600 73.2 700 57.6 800 47.5 900 40.2
Figure 39. Switching Frequency Selection
1000 34.8
1200 26.7
1400 21.5
1600 18.2
1800 15.8
2000 13.3
2200 11.8
Sequencing of Output Voltages
Some microprocessors and DSP chips need two power supplies with different voltage levels. These systems often require voltage sequencing between the core power supply and the I/O power supply. Without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processor's I/O ports or the I/O ports of a supporting system device such as memory, an FPGA or a data converter. To ensure that the I/O loads are not driven until the core voltage is properly biased, tracking of the core supply and the I/O supply voltage is necessary.
Designing a system without proper power supply sequencing for signal processing devices like DSPs, FPGAs, and PLDs may create risks as to reliability or proper functionality. The risk comes when there are active and inactive power supply rails on the device for a long time. During this time, the ESD structures, internal circuits and components are stressed from interference between different voltages (from the two separate power supply rails). When these conditions persist on multi-supply devices for long time periods (this is a cumulative phenomenon), the life of the products (DSP, FPGA, and
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PLD devices) is drastically reduced. The failure is often a result of high currents flowing to the pins or the high voltage difference between pins. In that case, the signal processors require multiple power supplies generating different voltage levels for core and I/O peripherals over time. NCP3123 offers ratiometric sequencing, sequential sequencing and tracking sections to manage the output voltages behavior during start-up and power-down. Basically, the DSP, FPGA, and PLD manufacturers do not specify the method of power sequencing, but they do specify restrictions on the time or voltage differences during power-up and power-down. The power-up sequence for microprocessors should be finished approximately within a few seconds to prevent the risks mentioned above. For more information, see the microprocessor manufacturers' datasheets.
AVIN C3 C13 R13
Ratiometric Sequencing
In the ratiometric sequencing mode, multiple outputs start ramping at the same time and also reach the regulation level at the same time. When common EN is pulled down, the output voltages are going down at the same time. See Figure 40. This functionality is created by using the same capacitor values as the soft-start capacitors for all outputs and by connecting all EN + SEQ pins together. To ensure this behavior, the soft start capacitors should have values greater than the time constant of the output inductor and output capacitor. For proper operation in this mode, using a common soft-start capacitor for both channels is not recommended.
VIN
C12 R_TRACK AVIN COMP1 AGND SS1 GND1 SW1 SW1 FB1 GND OUT1 SW1 VIN VIN VIN L11 D11 GND R12 C1 GND L21 D21 GND C22 R_T GND R23
VOUT1 VOUT2
PG1 Enable Disable EN1 PG2 EN1
R11
C11 GND GND OUT2
SEQ1 EN2 SEQ2 TRACK1
NCP3123
VIN VIN VIN
C2 GND
COMP2
AGND
GND2
SW2
SW2
TRACK2 FB2 RT
SW2
SS2
R21
C21 GND GND
R22 GND
C23 GND
Figure 40. Ratiometric Sequencing Configuration
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EN1/SEQ1 & EN2/SEQ2
SS1 & SS2
0.8V
4V
0.8V
VOUT1 & VOUT2
90% VFB1 (min) 90% VFB2 (min)
hyst + delay PG1 & PG2
Figure 41. Typical Behavior of Ratiometric Sequencing Mode
Figure 42. Ratiometric Mode - Power-up
Figure 43. Ratiometric Mode - Power-down
Figure 44. Ratiometric Mode - Start of OLM
Figure 45. Ratiometric Mode - End of OLM
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Sequential Sequencing (First-Up/Last-Down Sequence Configuration)
In sequential sequencing mode, the second output voltage starts ramping when the first output voltage is already settled and its power good signal is set. Figure 46 shows the NCP3123's configuration and standard waveforms. The rising slope of both voltages can be selected independently by the soft-start capacitors' values (C12, C22). When the
AVIN C3 C13 R13
enable pin is deactivated, the second output voltage decreases first, followed by the first output voltage. The control logic is based on the internal power good signal; no delay is added. The signal has the same threshold values as the power good signal shown in the electrical table. The sequential sequencing mode is also called first-up/ last-down and is ideal for DSPs with separate power supplies for the core and the I/O ports.
VIN
C12 R_TRACK AVIN COMP1 AGND SS1 GND1 SW1 SW1 FB1 GND OUT1 SW1 VIN VIN L11 D11 GND C1 GND L21 D21 GND C2 GND OUT2 R21 R11
PG1 Enable Disable EN1 PG2 EN1
C11 GND GND
SEQ1 EN2 SEQ2 TRACK1
NCP3123
VIN VIN VIN VIN
R12
COMP2
AGND
GND2
SW2
SW2
TRACK2 FB2 RT
SW2
SS2
C21 GND GND
C22 R_T GND GND
R22
R23 C23 GND
C12 C22
C22 C12
VOUT1 VOUT2
Figure 46. Sequential Configuration
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Daisy Chain Operation
The last-up/first-down power output has its SEQ pin tied to the EN of the first-up/last-down power output. Each output in the chain has its power-up delay set by the
soft-start ramp-up of the supply. This feeds its EN and its power-down delay set by the soft-start ramp-down of the supply that feeds its SEQ pin.
ENABLE DISABLE
SEQ
SS
C1
SEQ
SS
C2
SEQ
SS
C3
SEQ
SS
C4
EN NCP3123 TRACK
EN NCP3123 TRACK
EN NCP3123 TRACK
EN NCP3123 TRACK
Vout1 Vout2 Vout3 Vout4
C1 C2
C3 C4
C4 C3
C2 C1
Figure 47. Simplified Drawing of Daisy-chained NCP3123's
When the first voltage rail has reached a specific voltage level, the next voltage rail is enabled and its rise is monitored until it has reached the power good trip point. At this point, the next voltage rail is enabled. This continues until all
voltage rails have been enabled (see Figure 48). Power-down sequencing is just the opposite of the power-up sequence.
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EN1 & SEQ2
SS1
0.8V
90% VFB (min)
4V
0.8V
VOUT1
10% VFB (min)
Internal PG1
VOUT2
90% VFB (min)
10% VFB (min)
Internal PG2
SEQ1 & EN2
SS2
0.8V
4V
0.8V
VOUT1 & VOUT2
PG1
PG2
Figure 48. Typical Behavior of Sequential Mode
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NCP3123
Figure 49. Sequential Mode - Power-up
Figure 50. Sequential Mode - Power-down
Figure 51. Sequential Mode - Power-down
Figure 52. Daisy Chain of Four Outputs
Figure 53. OLM of the 3rd Output in Daisy Chain
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NCP3123
Tracking
Voltage tracking is enabled by applying a ramp voltage to the TRACK pin. When the voltage on the TRACK pin is below 0.8 V, the feedback voltage will regulate to this tracking voltage. When the tracking voltage exceeds 0.8 V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. In this start-up sequence, the tracking pin is used to match the output voltage ramps exactly. Higher output voltage will continue to rise past the lower regulated point. This is
AVIN C13 C3 R8
achieved by dividing the higher output voltage by the same ratio as the lower voltage feedback components and connecting the divided voltage into the TRACK pin of the lower voltage. Track pins must be tied high in the normal operation (except in the tracking mode). The output voltage during tracking can be calculated with the following equation:
V OUT + V TRACK 1 ) R5 R6 V TRACK t 0.8 V
VIN
Cmaster R10 AVIN COMP1 AGND SS1 GND1 SW1 SW1 FB1 GND OUT1 L1 D1 GND C9 GND C10 GND L2 D2 R11 GND GND R4 GND GND R1 C7 R2 R6 GND OUT2 R3 R5
PG1 Enable Disable PG2 EN1
SW1 VIN VIN VIN
SEQ1 EN2 SEQ2 TRACK1
NCP3123
VIN VIN VIN
GND GND
COMP2
AGND
GND2
SW2
SW2
TRACK2 FB2 RT
SW2
SS2
C8
R9 R7 C4 GND GND
Cmaster
VOUT1 VOUT2
Cmaster
Figure 54. Tracking Configuration
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EN1/SEQ1 & EN2/SEQ2
SS1
90% V (min)
FB1
0.8V
4V
0.8V
VOUT1 & SS2
TRACK2
90% V (min)
0.8V
FB1
0.8V
VOUT1 & VOUT2
90% V FB2 (min)
PG1
hyst+delay
PG2
hyst+delay
Figure 55. Typical Behavior of Tracking Configuration
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NCP3123
Figure 56. Tracking Mode - Power-up
Figure 57. Tracking Mode - Power-down
Figure 58. Tracking Mode of Four Outputs - Power-up
Figure 59. Tracking Mode of Four Outputs - Power-down
VOUT1
When hiccup overload mode is detected on the slave channel only, the output voltage of the 2nd channel (slave) decreases. After the overload condition ends, the slave channel voltage remains low. If the slave channel should rise when the OLM disappears, the configuration of the enable and soft-start pins shown in Figure 60 must be used.
EN2 pin
4k7 N-channel transistor
N-channel transistor SS2 pin CSS2 = 4n7
Figure 60. Augmented OLM in Tracking Mode
For proper operation of the modified tracking mode, use an SS1 capacitor with a value at least 10 times higher than that of the SS2 capacitor.
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Figure 61. Master Voltage - Start of OLM
Figure 62. Master Voltage - End of OLM
Figure 63. Master Voltage - Start of Augmented OLM
Figure 64. Master Voltage - End of Augmented OLM
Note: If the overload conditions are detected on the master channel only or on both channels together (master + slave),
both output voltages increase when the overload conditions are released.
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NCP3123
Mixed Mode A (Sequencing and Tracking) The different modes can also be used together to achieve various combinations of power sequencing. Mixed mode A demonstrates the configuration of tracking and sequencing for four outputs. The schematic and typical output behavior is shown in Figure 65. Mixed mode B shows the combination of tracking, sequencing and normal mode.
VIN C3 R8 R10 AVIN FB1 AGND COMP1 C5 SS1 GND1 SW1 SW1 GND SW1 VIN VIN VIN VIN VIN COMP2 VIN GND2 SW2 SW2 SS2 SW2 AGND C9 C10 OUT1 L1 D1 GND R1 R2 R5 R6 GND OUT2 R3 C8 GND GND
C13
Enable Disable
PG1 PG2 EN1
C7 GND GND
SEQ1 EN2 SEQ2 TRACK1 TRACK2 FB2 RT
NCP3123
GND GND L2 D2 GND R4
R9 GND R7 C4 GND GND
R11
C16
C1 R17
R21 AVIN FB1 AGND COMP1
C6 SS1 GND1 SW1 SW1
GND SW1 VIN VIN VIN VIN VIN C14 C15 VIN OUT1 L3 D4 GND R12 R13 R19 R20 GND OUT2 R14 C12 GND GND
PG1 PG2 EN1
VOUT1 VOUT2 VOUT3 VOUT4
C11 GND GND
SEQ1 EN2 SEQ2 TRACK1 TRACK2 FB2 RT
NCP3123
COMP2
AGND
GND2
SW2
SW2
SS2
SW2
GND GND L4 D3 GND R15
R18 GND R16 C2 GND GND
R22
Figure 65. Mixed Mode, Configuration A http://onsemi.com
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NCP3123
Figure 66. Mixed Mode of Four Outputs - Power-up
Figure 67. Mixed Mode of Four Outputs - Power-down
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NCP3123
Mixed Mode B (Normal & Sequencing & Tracking)
ENABLE DISABLE Tied high Out1 EN OUT SEQ NCP3123 TRACK Out2 EN OUT SEQ NCP3123 TRACK
Out3 EN OUT SEQ NCP3123 TRACK Out4 EN OUT SEQ NCP3123 TRACK
Out5 EN OUT SEQ NCP3123 TRACK Out6 EN OUT SEQ NCP3123 TRACK
VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6
Figure 68. Mixed Mode, Configuration B
Figure 69. Mixed Mode of Six Outputs - Power-up
Figure 70. Mixed Mode of Six Outputs - Power-down
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Normal Operation (No Tracking, No Sequencing)
AVIN C3 C13 R13 VIN
R24 R_TRACK
R14
C12 GND
AVIN
COMP1
AGND
SS1
GND1
FB1
SW1
SW1
OUT1 SW1 VIN VIN VIN L11 D11 GND R12 C1 GND L21 D21 GND C2 GND OUT2 R21 GND GND R11 C11
PG1 Enable Disable Enable Disable EN2 PG2 EN1
PG1 PG2 EN1
SEQ1 EN2 SEQ2 TRACK1
NCP3123
VIN VIN VIN
COMP2
AGND
GND2
SW2
SW2
TRACK2 FB2 RT
SW2
SS2
C21 GND GND
C22 RT GND R23 C23 VOUT1 VOUT2 GND GND
R22
Figure 71. Normal Operation Configuration
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EN1/SEQ1
EN2/SEQ2
SS1
0.8V
4V
0.8V
SS2
0.8V 90%VFB (min)
4V
0.8V
VOUT1
VOUT2
90%VFB (min)
hyst + delay PG1
PG2
hyst + delay
Figure 72. Typical Application Behavior
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NCP3123
Parallel Operation OLM in Parallel Operation
Parallel operation of NCP3123 circuit(s) has several advantages. One of the most important aspects is the capability to deliver a double output current. The major advantage is a reduced output voltage ripple in case of out-of-phase synchronization. The standard configuration is shown in Figure 73.
AVIN C3 C13 R13
When OLM is detected (e.g., a jump from 4 A on the output to 6 A), the output voltage decreases. When OLM wears off, the output current must be decreased below 3.5 A. Then, the output voltage is released and current can be increased again - up to 4 A.
VIN
C12 R_TRACK AVIN COMP1 AGND SS1 GND1 FB1 SW1 SW1 GND OUT L11 D11 GND R12 C1 GND L21 D21 GND C22 RT GND R23 C23 GND GND C2 GND GND GND R11 C11
PG1 Enable Disable EN PG2 EN1
SW1 VIN VIN VIN
SEQ1 EN2 SEQ2 TRACK1 COMP2 AGND GND2 SW2 SW2 TRACK2 FB2 RT SS2
NCP3123
VIN VIN VIN SW2
Figure 73. Parallel Operation Configuration.
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Figure 74. Parallel Operation of Both Outputs
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NCP3123
Loop Compensation
A COMP pin of the transconductance error amplifier is used to compensate the regulation control system. Standard COMP pin values are shown in the BOM at the end of the datasheet. (See the COMPCALC program to determine customer preferred values.) To design the compensation components for conditions not described in Table 6 and/or for tuning the compensation
Vin [V] 12 12 5 Vout [V] 3.3 5 1.8 Freq [kHz] 200 200 200 Iout [A] 3 3 3 L11 [mH] 15 22 10
for specific requirements, the COMPCALC design tool is available from ON Semiconductor at no charge. Visit http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP to download the self-extracting program for NCP3123 loop compensation design assistance. There is an Excel design tool for component selection. This design tool is available at http://www.onsemi.com/pub/Collateral/NCP312X%20 DWS.XLS.
C13 [nF] 22 18 27 R13 [kW] 4.7 4.7 2.7 C14 [pF] 220 270 270 R14 [W] 100 100 100 C15 [nF] none none none
Table 6. Compensation Values Example for Typical Output Voltages
C11 - ceramic [mF] 22 22 22
Thermal Considerations
The NCP3123 has thermal shutdown protection to safeguard the device from overheating when the die temperature exceeds 160_C. For the best thermal performance, wide copper traces and a generous amount of PCB printed circuit board copper should be used in the board layout. One exception to this is at the SW switching node, which should not have a large area in order to minimize the EMI radiation and other parasitic effects. Large areas of copper provide the best transfer of heat from the IC into the ambient air.
PCB Layout Guidelines
As in any switching regulator, the layout of the printed circuit board is very important. Rapidly switching currents associated with wiring inductance, stray capacitance and parasitic inductance of the printed circuit board traces can generate voltage transients that can generate electromagnetic interferences (EMI) and affect the desired operation. To minimize inductance and ground loops, the lengths of the leads indicated by heavy lines should be kept as short as possible. For best results, single-point grounding or ground plane construction should be used. On the other hand, the PCB area connected to the SW pin (drain of the internal switch) of the circuit should be kept to a minimum in order to minimize coupling to sensitive circuitry. Another sensitive part of the circuit is the feedback. It is important to keep the sensitive feedback wiring short. To ensure this, physically locate the programming resistors near the regulator. There should be a ground area on the top layer directly under the IC with an exposed area for connecting the IC exposed pad. Any internal ground planes should be connected by vias to this ground area. Additional vias must be used at the ground side of the input and output capacitors. The GND pin also should be tied to the PCB ground in the area under the IC.
When laying out the buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the circuit: 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of sensitive ground connections. 3. Avoid ground loops, as they pick up noise. Use star or single-point grounding. 4. For high power buck regulators on double-sided PCBs, a single ground plane (usually the bottom) is recommended. 5. Even though double-sided PCBs are usually sufficient for a good layout, four layer PCBs represent the optimum approach to reducing susceptibility to noise. Use the two internal layers as the power and GND planes, the top layer for power connections and component vias, and the bottom layer for noise sensitive traces. 6. Keep the inductor switching node small by placing the output inductor as close as possible to the chip. 7. Use fewer, but larger, output capacitors; keep the capacitors clustered; and use multiple layer traces with heavy copper to keep the parasitic resistance low. 8. Place the output capacitors as close to the output coil as possible. 9. Place the COMP capacitor as close as possible to the COMP pin. 10. Place the VIN bypass capacitors as close as possible to the IC. 11. Place the RT resistor as close as possible to the RT pin. 12. The exposed pad must be connected to a ground plane with a large copper surface area to dissipate heat.
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NCP3123
Layout Diagram
Figure 75. Typical Layout Diagram
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NCP3123
Typical Application Circuit
C3 100n
C13 22n R13 4.7k
C15 NU RVIN 100
VIN
R1 75k
R26 3.3k
R16 5.1k AVIN COMP1 AGND FB1
C12 100n GND GND1 SW1 SW1 L11 SW1 VIN VIN VIN 3.3u D11 MBRS340 GND C1 22u C2 100n R14 100 R11 68k C14 220p R12 13k OUT1 3A @ 5V SS1
PG1 Enable Disable Enable Disable EN2 PG2 EN1
PG1 PG2 EN1
C11 22u
SEQ1 EN2 SEQ2 TRACK1
NCP3123
VIN VIN VIN
GND OUT2 3A @ 3.3V
GND GND L21 3.3u D21 MBRS340 GND C24 220p
GND R21 47k R22 15k
COMP2
AGND
GND2
SW2
SW2
TRACK2 FB2 RT
SW2
SS2
C22 100n GND
R24 100
C21 22u
GND GND
R23 4.7k C23 22n GND
C25 NU
Figure 76. Typical Circuit Diagram
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NCP3123
Figure 77. PCB Layout Example - Evaluation Board v 2.11
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NCP3123
Components: Table 7. Bill of Materials for the Typical Application Circuit
BOM of the NCP3123 - Evaluation Board v2.11
Qty
Value
Scale
Ref. Designator Chip
Vendor
Part number
1
QFN32, 5x5 mm
NCP3123 Resistors
ON Semiconductor
3 1 1 1 2 1 1 1 1
100 75 68 13 4.7 47 15 5.1 3.3
W kW kW kW kW kW kW kW kW
1206 1206 1206 1206 1206 1206 1206 1206 1206
RVIN, R14, R24 R1 R11 R12 R13, R23 R21 R22 R16 R26 Capacitors
Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay
RCA1206100R0FKEA RCA120675KFKEA RCA120668K0FKEA RCA120613K0FKEA RCA12064K70FKEA RCA120647K0FKEA RCA120615K0FKEA RCA12065K10FKEA RCA12063K30FKEA
3 4 2 2
22 100 22 220
mF nF nF pF
1210 1206 1206 1206
C1, C11, C21 C2, C3, C12, C22 C13, C23 C14, C24 Inductors
Kemet Epcos Epcos Epcos
C1210C226K4PAC B37872A5104K060 B37872A5223K060 B37871K5221J060
2
3.3
mH
L11, L21 Diodes
Coilcraft
DS3316P-332
2
MBRS340T3
D11, D21
ON Semiconductor
ORDERING INFORMATION
Device NCP3123MNTXG Package QFN32 (Pb-Free) Shipping 4000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
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NCP3123
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D
A B
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
1 32 X b 0.10 C A B 32 25
0.05 C BOTTOM VIEW
32 X
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE
TOP VIEW SIDE VIEW
9
PIN ONE LOCATION
E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
D2
K
17 32 X
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
E2
24
e
3.20
5.30
0.28
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP3123/D

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